buffer interface between tester and target board

[jayken]

Hi, got myself a boundary testing device and mainboard and want to create a breadboarded interface between the two to protect the target from any issues that crop up from our tester, which has been faulty in the past.

Any tips on how I can design this with npn transitors?

 

[IRstuff]

Why wouldn't you just use a buffer of the same ilk as those in the tester?

TTFN

FAQ731-376

 

[jayken]

been trying to pry that information out of corelis but they won't budge

 

[jayken]

there is a 33kohm resistor that goes to each of the TAP connections to bring current down, no other protection. That should be enough, but I would like another layer.

 

[IRstuff]

Well, you should use integrated buffer chips, if nothing else, duplicate the I/O buffers on your board. You're not going to be able to build meaningfully performing buffers out of discrete transistors, unless you're running an absurdly low clock rate system.

TTFN

FAQ731-376