Recent content by homoly

Hi, I will try to post the sag if I can find. After a few measurements I have realized the distorsion comes from turning on the second 12V power supply which is a prerequisity the swap between the clock. I can post also the the schematics of the the supplies ( standard diode bridge/LM7812 and...

Scotty, thank you very much for the tips , I will check them out even if it seems to be a time consuming task :)

Hi Scotty, I am especially Interested in AC/DC capacitors in power systems or UPS units and the power semiconductors ( IGBTs, SCRs... ) and their driver circuits maybe also batteries of the backup systems, arc flash hazard and so on. So some literature for power electronic which is similar...

I would like to ask you if you could recommend me some good book(s) which would be useful for failure analysis of the components failed in field. Ideally the description of the potential failure mechanism for different component types, maybe some hints and troubleshooting and localizing the...

Hello Keith, The voltage is 12V. OK thanks for the suggestion, I can try to connect the 120ohm resistor across the load ( as a pull down between the CMOS input and the GND ) but at first sight the 120 Ohm value seems to be too low to be driven directly with the output of the CMOS AND gate...

Hello, I would need some advice with one problem related to clock signal picking up noise. First the layout. The source of the clock signals ( actually 2 identical clocks which are complementar to each other and are selected by logic ) is gated 555 output of 22kHz by CMOS AND gate. The target...

Thanks Noway2, so the good news is that the resistor can prevent also the diodes during transient overvoltage or accidental wrong voltage application within some reasonable limits :). So if I get it from information above correctly the resistor sizing consideration for interfacing should be...

So it seems the 10k value is selected to provide safe enough output current for the most commonly used comparators in the case of permanent short of CMOS input to ground ( I was not sure if this should suppose to prevent the ESD diodes from overloading when they are activated by ringing from the...

OK the ESD point of view is more or less clear now. But what is the mening of 10K capacitor between comparator and CMOS. My idea is now the ESD diodes and the resistor creates a lowest possible resistance for a very short duration ESD which current is decreasing in time (as for capacitor...

OK so the material in the http://www.ecelab.com/interfacing-opamp-ttl-cmos.htm is no properly describing the situation as according this information the 10k resistor is not necessary. Yes I was talking about ESD diodes ( or maybe for some ICs the reverse polarity protection ). Normal operation...

Thank you for the entries, I have found the app note I was talking about related to discrete Mosfet paralleling: http://www.microsemi.com/micnotes/APT0402.pdf. Benta, thanks this current value now makes a sense for me with 10k resistor. The LM339 is OC indeed, I have connected the pull-up to...

This is clear in principle, but as I mentioned before I have checked the http://www.fairchildsemi.com/ds/CD/CD4013BC.pdf and only parameter I have found is IIN = 1uA. This seems to me like a steady state maximum current given by a "worst case gate". If I would calculate the limited current for...

OK so basically the current limiter resistor should help when the 2 12V sources should be referred to different grounds with a level shift at least 0.7V activating the clamping diodes and also to limit current when there is voltage on eventually not powered IC ( sequencing during turn ons and...

Hello, I have been involved in modifications on the existing device using CMOS ICs with which I do not have practical experience and for this reason I would like to ask few questions. In new circuit I would have to connect the output of LM339 with CD4013B flip flop. I have found article...

Thank you for the response. Gabriel.